Microcontroller User's Manual

MOTOROLA Appendix A. Register Memory Map A-3
Table A-3. Register Memory Map
Address Name Mnemonic Size
SCM Registers
IPSBAR + 0x000 Internal Peripheral System Base Address Register IPSBAR 32
IPSBAR + 0x008 Copy of RAMBAR RAMBAR 32
IPSBAR + 0x00C Reserved —
IPSBAR + 0x010 Core Reset Status Register CRSR 8
IPSBAR + 0x011 Core Watchdog Control Register CWCR 8
IPSBAR + 0x012 Low-Power Interrupt Control Register LPICR 8
IPSBAR + 0x013 Core Watchdog Service Register CWSR 8
IPSBAR + 0x014 DMA Request Control Register DMAREQC 32
IPSBAR + 0x01C Bus Master Park Register MPARK 32
IPSBAR + 0x020 Master Privilege Register MPR 32
IPSBAR + 0x024 Peripheral Access Control Register 0 PACR0 8
IPSBAR + 0x025 Peripheral Access Control Register 1 PACR1 8
IPSBAR + 0x026 Peripheral Access Control Register 2 PACR2 8
IPSBAR + 0x027 Peripheral Access Control Register 3 PACR3 8
IPSBAR + 0x028 Peripheral Access Control Register 4 PACR4 8
IPSBAR + 0x02A Peripheral Access Control Register 5 PACR5 8
IPSBAR + 0x02B Peripheral Access Control Register 6 PACR6 8
IPSBAR + 0x02C Peripheral Access Control Register 7 PACR7 8
IPSBAR + 0x02E Peripheral Access Control Register 8 PACR8 8
IPSBAR + 0x030 Grouped Peripheral Access Control Register 0 GPACR0 8
IPSBAR + 0x031 Grouped Peripheral Access Control Register 1 GPACR1 8
SDRAMC Registers
IPSBAR + 0x040 DRAM Control Register DCR 16
IPSBAR + 0x048 DRAM Address and Control Register 0 DACR0 32
IPSBAR + 0x04C DRAM Mask Register Block 0 DMR0 32
IPSBAR + 0x050 DRAM Address and Control Register 1 DACR1 32
IPSBAR + 0x054 DRAM Mask Register Block 1 DMR1 32
Chip Select Registers
IPSBAR + 0x080 Chip Select Address Register 0 CSAR0 16
IPSBAR + 0x084 Chip Select Mask Register 0 CSMR0 32
IPSBAR + 0x08A Chip Select Control Register 0 CSCR0 16
IPSBAR + 0x08C Chip Select Address Register 1 CSAR1 16
IPSBAR + 0x092 Chip Select Mask Register 1 CSMR1 32
IPSBAR + 0x094 Chip Select Control Register 1 CSCR1 16