Microcontroller User's Manual

2-6 MCF5282 User’s Manual MOTOROLA
Processor Register Description
• Two 32-bit access control registers (ACR0, ACR1)
• Two 32-bit memory base address registers (RAMBAR, FLASHBAR)
Figure 2-5. Supervisor Programming Model
The following paragraphs describe the supervisor programming model registers.
2.2.3.1 Status Register (SR)
The SR stores the processor status and includes the CCR, the interrupt priority mask, and
other control bits. In supervisor mode, software can access the entire SR. In user mode, only
the lower 8 bits are accessible (CCR). The control bits indicate the following states for the
processor: trace mode (T bit), supervisor or user mode (S bit), and master or interrupt state
(M bit). All defined bits in the SR have read/write access when in supervisor mode.
System Byte Condition Code Register (CCR)
151413121110 876543210
T0SM0 I 000XNZVC
Figure 2-6. Status Register
Table 2-2. SR Field Descriptions
Bits Name Description
15 T Trace enable. When set, the processor performs a trace exception after
every instruction.
14 — Reserved, should be cleared.
13 S Supervisor/user state. Denotes whether the processor is in supervisor
mode (S = 1) or user mode (S = 0).
SR
15 7 0
31
STATUS
(CCR)
OTHER_A7
SUPERVISOR A7
STACK POINTER
VBR
VECTOR BASE
REGISTER
CACR
CACHE
CONTROL
ACR0
ACCESS
CONTROL
ACR1
ACCESS
CONTROL
FLASHBAR
FLASH BASE
ADDRESS REGISTER
RAMBAR
RAM BASE
ADDRESS REGISTER