Microcontroller User's Manual

33-20 MCF5282 User’s Manual MOTOROLA
Fast Ethernet AC Timing Specifications
Table 33-16 lists specifications for the I
2
C output timing parameters shown in Figure 33-9.
Figure 33-9 shows timing for the values in Table 33-15 and Table 33-16.
Figure 33-9. I
2
C Input/Output Timings
33.12 Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at either 5.0 V or
3.3 V.
Table 33-16. I
2
C Output Timing Specifications between SCL and SDA
Num Characteristic Min Max Units
I1
1
1
Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed
with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in
Table 33-16. The I
2
C interface is designed to scale the actual data transition time to move it to
the middle of the SCL low period. The actual position is affected by the prescale and division
values programmed into the IFDR; however, the numbers given in Table 33-16 are minimum
values.
Start condition hold time 6 — Bus clocks
I2
1
Clock low period 10 — Bus clocks
I3
2
2
Because SCL and SDA are open-collector-type outputs, which the processor can only actively
drive low, the time SCL or SDA take to reach a high level depends on external signal
capacitance and pull-up resistor values.
SCL/SDA rise time (V
IL
= 0.5 V to V
IH
= 2.4 V) — — µS
I4
1
Data hold time 7 — Bus clocks
I5
3
3
Specified at a nominal 50-pF load.
SCL/SDA fall time (V
IH
= 2.4 V to V
IL
= 0.5 V) — 3 ns
I6
1
Clock high time 10 — Bus clocks
I7
1
Data setup time 2 — Bus clocks
I8
1
Start condition setup time (for repeated start
condition only)
20 — Bus clocks
I9
1
Stop condition setup time 10 — Bus clocks
I2 I6
I1 I4
I7
I8 I9
I5
I3
SCL
SDA