Microcontroller User's Manual

MOTOROLA Chapter 33. Electrical Characteristics 33-19
I
2
C Input/Output Timing Specifications
Figure 33-8. RSTI and Configuration Override Timing
33.11 I
2
C Input/Output Timing Specifications
Table 33-15 lists specifications for the I
2
C input timing parameters shown in Figure 33-9.
R5 RSTO valid to Config. Overrides valid t
ROVCV
0—ns
R6 Configuration Override Setup Time to RSTO
invalid t
COS
20 — t
CYC
R7 Configuration Override Hold Time after RSTO invalid t
COH
0—ns
R8 RSTO invalid to Configuration Override High Impedance t
ROICZ
—1t
CYC
1
All AC timing is shown with respect to 50% V
DD
levels unless otherwise noted.
2
During low-power STOP, the synchronizers for the RSTI input are bypassed and RSTI is asserted asynchronously to
the system. Thus, RSTI
must be held a minimum of 100 ns.
Table 33-15. I
2
C Input Timing Specifications between SCL and SDA
Num Characteristic Min Max Units
I1 Start condition hold time 2 — Bus clocks
I2 Clock low period 8 — Bus clocks
I3 SCL/SDA rise time (V
IL
= 0.5 V to V
IH
=2.4 V) — 1 mS
I4 Data hold time 0 — ns
I5 SCL/SDA fall time (V
IH
= 2.4 V to V
IL
= 0.5 V) — 1 mS
I6 Clock high time 4 — Bus clocks
I7 Data setup time 0 — ns
I8 Start condition setup time (for repeated start condition only) 2 — Bus clocks
I9 Stop condition setup time 2 — Bus clocks
Table 33-14. Reset and Configuration Override Timing (Continued)
(V
DD
= 2.7 to 3.6 V, V
SS
= 0 V)
1
NUM Characteristic Symbol Min Max Unit
R1
R2
CLKOUT
RSTI
RSTO
R3
R4
R8
R7R6R5
Configuration Overrides:
R4
(RCON, Override pins)