Microcontroller User's Manual

2-4 MCF5282 User’s Manual MOTOROLA

Processor Register Description

Figure 2-2. User Programming Model

2.2.1.5 Condition Code Register (CCR)

The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for

results generated by processor operations. Bit 4, the extend bit (X bit), is also used as an

input operand during multiprecision arithmetic computations.

43210

XNZVC

Figure 2-3. Condition Code Register (CCR)

Table 2-1. CCR Field Descriptions

Bits Name Description

4 X Extend condition code bit.

3 N Negative condition code bit. Set if the most significant bit of the result is set;

otherwise cleared.

2 Z Zero condition code bit. Set if the result equals zero; otherwise cleared.

1 V Overflow condition code bit. Set if an arithmetic overflow occurs implying that the

result cannot be represented in the operand size; otherwise cleared.

0 C Carry condition code bit. Set if a carry out of the operand msb occurs for an

addition, or if a borrow occurs in a subtraction; otherwise cleared

Set to the value of the C bit for arithmetic operations; otherwise not affected.

CCR

15 7 0

15 031

DATA

REGISTERS

ADDRESS

REGISTERS

USERSTACK

POINTER

PROGRAM

COUNTER

CONDITION

CODE