Microcontroller User's Manual

MOTOROLA Chapter 2. ColdFire Core 2-1
Chapter 2
ColdFire Core
This section describes the organization of the Version 2 (V2) ColdFire
®
processor core and
an overview of the program-visible registers. For detailed information on instructions, see
the ColdFire Family Programmer’s Reference Manual.
2.1 Processor Pipelines
Figure 2-1 is a block diagram showing the processor pipelines of a V2 ColdFire core.
Figure 2-1. ColdFire Processor Core Pipelines
Instruction
Instruction
FIFO
Decode & Select,
Address
read_data[31:0]
IAG
IC
IB
DSOC
AGEX
Address [31:0]
Instruction Buffer
Address
Generation
Fetch Cycle
Generation,
Execute
Operand Fetch
Operand
Execution
Pipeline
Instruction
Fetch
Pipeline
write_data[31:0]