Microcontroller User's Manual

MOTOROLA Chapter 29. Debug Support 29-35
Background Debug Mode (BDM)
Command Sequence:
Figure 29-36. WCREG Command Sequence
Operand Data: This instruction requires two longword operands. The first selects
the register to which the operand data is to be written; the second
contains the data.
Result Data: Successful write operations return 0xFFFF. Bus errors on the write
cycle are indicated by the setting of bit 16 in the status message and
by a data pattern of 0x0001.
29.5.3.3.11 Read Debug Module Register (
RDMREG)
Read the selected debug module register and return the 32-bit result. The only valid register
selection for the
RDMREG command is CSR (DRc = 0x00). Note that this read of the CSR
clears CSR[FOF, TRG, HALT, BKPT]; as well as the trigger status bits (CSR[BSTAT]) if
either a level-2 breakpoint has been triggered or a level-1 breakpoint has been triggered and
no level-2 breakpoint has been enabled.
Command/Result Formats:
Table 29-20 shows the definition of DRc encoding.
15 12 11 8 7 5 4 0
Command 0x2 0xD 100 DRc
Result D[31:16]
D[15:0]
Figure 29-37. RDMREG Command/Result Formats
XXX
’NOT READY’
WCREG
???
MS ADDR
’NOT READY’
MS ADDR
’NOT READY’
WRITE
CONTROL
REGISTER
NEXT CMD
’CMD COMPLETE’
MS DATA
’NOT READY’
NEXT CMD
’NOT READY’
XXX
BERR
LS DATA
’NOT READY’