Microcontroller User's Manual
MOTOROLA Chapter 29. Debug Support 29-21
Background Debug Mode (BDM)
29.5.3.1 ColdFire BDM Command Format
All ColdFire Family BDM commands include a 16-bit operation word followed by an
optional set of one or more extension words, as shown in Figure 29-15.
Table 29-18 describes BDM fields.
29.5.3.1.1 Extension Words as Required
Some commands require extension words for addresses and/or immediate data. Addresses
require two extension words because only absolute long addressing is permitted. Longword
accesses are forcibly longword-aligned and word accesses are forcibly word-aligned.
Immediate data can be 1 or 2 words long. Byte and word data each requires a single
extension word and longword data requires two extension words.
Operands and addresses are transferred most-significant word first. In the following
descriptions of the BDM command set, the optional set of extension words is defined as
address, data, or operand data.
15 1098765432 0
Operation 0 R/W Op Size 0 0 A/D Register
Extension Word(s)
Figure 29-15. BDM Command Format
Table 29-18. BDM Field Descriptions
Bit Name Description
15–10 Operation Specifies the command. These values are listed in Table 29-17.
9 0 Reserved, should be cleared.
8 R/W Direction of operand transfer.
0 Data is written to the CPU or to memory from the development system.
1 The transfer is from the CPU to the development system.
7–6 Op Size Operand data size for sized operations. Addresses are expressed as 32-bit absolute values. Note that a
command performing a byte-sized memory read leaves the upper 8 bits of the response data undefined.
Referenced data is returned in the lower 8 bits of the response.
Operand Size Bit Values
00 Byte 8 bits
01 Word 16 bits
10 Longword 32 bits
11 Reserved —
5–4 00 Reserved, should be cleared.
3 A/D Address/data. Determines whether the register field specifies a data or address register.
0 Indicates a data register.
1 Indicates an address register.
2–0 Register Contains the register number in commands that operate on processor registers.










