Microcontroller User's Manual

MOTOROLA Chapter 29. Debug Support 29-13
Programming Model
Table 29-9 describes DBR fields.
Table 29-10 describes DBMR fields.
The DBR supports both aligned and misaligned references. Table 29-11 shows
relationships between processor address, access size, and location within the 32-bit data
bus.
29.4.6 Program Counter Breakpoint/Mask Registers
(PBR, PBMR)
The PBR defines an instruction address for use as part of the trigger. This register’s contents
are compared with the processor’s program counter register when TDR is configured
appropriately. PBR bits are masked by setting corresponding PBMR bits. Results are
compared with the processor’s program counter register, as defined in TDR. Figure 29-9
shows the PC breakpoint register.
Table 29-9. DBR Field Descriptions
Bits Name Description
31–0 Data Data breakpoint value. Contains the value to be compared with the data value from the processor’s local bus
as a breakpoint trigger.
Table 29-10. DBMR Field Descriptions
Bits Name Description
31–0 Mask Data breakpoint mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBR bit allows the
corresponding DBR bit to be compared to the appropriate bit of the processor’s local data bus. Setting a
DBMR bit causes that bit to be ignored.
Table 29-11. Access Size and Operand Data Location
A[1:0] Access Size Operand Location
00 Byte D[31:24]
01 Byte D[23:16]
10 Byte D[15:8]
11 Byte D[7:0]
0x Word D[31:16]
1x Word D[15:0]
xx Longword D[31:0]