Microcontroller User's Manual

29-8 MCF5282 User’s Manual MOTOROLA
Programming Model
29.4.2 Address Attribute Trigger Register (AATR)
The AATR, shown in Figure 29-5, defines address attributes and a mask to be matched in
the trigger. The register value is compared with address attribute signals from the
processor’s local high-speed bus, as defined by the setting of the trigger definition register
(TDR).
Table 29-5 describes AATR fields
.
15 14 13 12 11 10 8 7 6 5 4 3 2 0
Field RM SZM TTM TMM R SZ TT TM
Reset 0000_0000_0000_0101
R/W Write only. AATR is accessible in supervisor mode as debug control register 0x06 using the WDEBUG instruction
and through the BDM port using the WDMREG command.
DRc[4–0] 0x06
Figure 29-5. Address Attribute Trigger Register (AATR)
Table 29-5. AATR Field Descriptions
Bits Name Description
15 RM Read/write mask. Setting RM masks R in address comparisons.
14–13 SZM Size mask. Setting an SZM bit masks the corresponding SZ bit in address comparisons.
12–11 TTM Transfer type mask. Setting a TTM bit masks the corresponding TT bit in address comparisons.
10–8 TMM Transfer modifier mask. Setting a TMM bit masks the corresponding TM bit in address comparisons.
7 R Read/write. R is compared with the R/W
signal of the processor’s local bus.
6–5 SZ Size. Compared to the processor’s local bus size signals.
00 Longword
01 Byte
10 Word
11 Reserved
4–3 TT Transfer type. Compared with the local bus transfer type signals.
00 Normal processor access
01 Reserved
10 Emulator mode access
11 Acknowledge/CPU space access
These bits also define the TT encoding for BDM memory commands. In this case, the 01 encoding indicates
an external or DMA access (for backward compatibility). These bits affect the TM bits.