Microcontroller User's Manual

MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) 27-29
Register Descriptions
27.6.8 Result Registers
The result word table is a 64 half-word (128 byte) long by 10-bit wide RAM. An entry is
written by the QADC after completing an analog conversion specified by the corresponding
CCW table entry.
27.6.8.1 Right-Justified Unsigned Result Register (RJURR)
Table 27-17. Multiplexed Channel Assignments and Signal Designations
Multiplexed Input Signals
Channel Number
1
in CCW CHAN Field
1
All channels not listed are reserved or unimplemented and return undefined results.
Port Signal
Name
Analog
Signal Name
Other
Functions
Signal Type Binary Decimal
PQB0
PQB1
PQB2
PQB3
ANW
ANX
ANY
ANZ
—
—
—
—
Input
Input
Input
Input
000XX0
000XX1
010XX0
010XX1
0, 2, 4, 6
1, 3, 5, 7
16, 18, 20, 22
17, 19, 21, 23
PQA0
PQA1
—
—
MA0
MA1
Output
Output
—52
53
PQA3
PQA4
AN55
AN56
ETRIG1
ETRIG2
Input/Output
Input/Output
110111
111000
55
56
V
RL
V
RH
—
Low Reference
High Reference
—
—
—
(V
RH
–V
RL
)/2
Input
Input
—
111100
111101
111110
60
61
62
— — End-of-Queue Code — 111111 63
15 10 9 8
Field — RESULT
Reset 0000_00 Undefined
R/W: R R/W
7 0
Field RESULT
Reset Undefined
R/W: R/W
Address IPSBAR + 0x19_0280, 0x19_02fe
Figure 27-15. Right-Justified Unsigned Result Register (RJURR)