Microcontroller User's Manual

MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) 27-27

the current CCW. The bits in this register are read anytime (except during stop mode), write

anytime (except during stop mode).

15 10 9 8

Field — P BYP

Reset 0000_00 Unaffected

R/W: R R/W

7 6 5 4 3210

Field IST1 IST0 CHAN5 CHAN4 CHAN3 CHAN2 CHAN1 CHAN0

Reset Undefined

R/W: R

Address IPSBAR + 0x19_0200, 0x19_027e

Figure 27-14. Conversion Command Word Table (CCW)

Table 27-14. CCW Field Descriptions

Bit(s) Name Description

15–10 — Reserved, should be cleared.

9 P Pause. Allows subqueues to be created within queue 1 and queue 2. The QADC performs the

conversion specified by the CCW with the pause bit set and then the queue enters the pause

state. Another trigger event causes execution to continue from the pause to the next CCW.

1 Enter pause state after execution of current CCW.

0 Do not enter pause state after execution of current CCW.

NOTE: The P bit does not cause the queue to pause in software-initiated modes or externally

gated modes.

8 BYP Sample amplifier bypass. Enables the amplifier bypass mode for a conversion and subsequently

changes the timing. The initial sample time is eliminated, reducing the potential conversion

time by two QCLKs. However, due to internal RC effects, a minimum final sample time of four

QCLKs must be allowed. When using this mode, the external circuit should be of low source

impedance. Loading effects of the external circuitry need to be considered because the benefits

of the sample amplifier are not present.

1 Amplifier bypass mode enabled

0 Amplifier bypass mode disabled

NOTE: BYP is maintained for software compatibility but has no functional benefit on this

version of the QADC.