Microcontroller User's Manual

MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) 27-17

If BQ2[6:0] is changed while queue 1 is active, the effect of BQ2[6:0] as an end-of-queue

indication for queue 1 is immediate. However, beware of the risk of losing the end-of-queue

1 when changing BQ2[6:0]. Using EOQ (channel 63) to end queue 1 is recommended.

NOTE

If BQ2[6:0] was assigned to the CCW that queue 1 is currently

working on, then that conversion is completed before the

change to BQ2[6:0] takes effect.

Each time a CCW is read for queue 1, the CCW location is compared with the current value

of the BQ2[6:0] pointer to detect a possible end-of-queue condition. For example, if

BQ2[6:0] is changed to CCW3 while queue 1 is converting CCW2, queue 1 is terminated

after the conversion is completed. However, if BQ2[6:0] is changed to CCW1 while queue

1 is converting CCW2, the QADC would not recognize a BQ2[6:0] end-of-queue condition

until queue 1 execution reached CCW1 again, presumably on the next pass through the

queue.

Stop mode resets this register (0x007f)

15 14 13 12 11 10 9 8

Field CIE2 PIE2 SSE2 MQ212 MQ211 MQ210 MQ29 MQ28

Reset 0000_0000

R/W: R/W

7 6 5 4 3210

Field RESUME BQ26 BQ25 BQ24 BQ23 BQ22 BQ21 BQ20

Reset 0111_1111

R/W: R/W

Address IPSBAR + 0x19_000e, 0x19_000f

Figure 27-10. QADC Control Register 2 (QACR2)