Microcontroller User's Manual

MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) 27-11

NOTE

Use caution when mixing digital and analog inputs. They

should be isolated as much as possible. Rise and fall times

should be as large as possible to minimize ac coupling effects.

27.6.5 Control Registers

This subsection describes the QADC control registers.

27.6.5.1 QADC Control Register 0 (QACR0)

QACR0 establishes the QADC sampling clock (QCLK) with prescaler parameter fields and

defines whether external multiplexing is enabled. Typically, these bits are written once

when the QADC is initialized and not changed thereafter. The bits in this register are read

anytime, write anytime (except during stop mode).

76543210

Field — DDQA4 DDQA3 — DDQA1 DDQA0

Reset 0000_0000

R/W: R R/W R R/W

Address IPSBAR + 0x19_0008

Figure 27-6. QADC Port QA Data Direction Register (DDRQA)

76543210

Field — DDQB3 DDQB2 DDQB1 DDQB0

Reset 0000_0000

R/W R

Address IPSBAR + 0x19_0009

Figure 27-7. Port QB Data Direction Register (DDRQB)