Microcontroller User's Manual

MOTOROLA Chapter 27. Queued Analog-to-Digital Converter (QADC) 27-7
Memory Map
27.4.6 Voltage Reference Signals
V
RH
and V
RL
are the dedicated input signals for the high and low reference voltages.
Separating the reference inputs from the power supply signals allows for additional external
filtering, which increases reference voltage precision and stability, and subsequently
contributes to a higher degree of conversion accuracy.
NOTE
V
RH
and V
RL
must be set to V
DDA
and V
SSA
potential,
respectively. For more information, refer to Section 27.9.
27.4.7 Dedicated Analog Supply Signals
The V
DDA
and V
SSA
signals supply power to the analog subsystems of the QADC module.
Dedicated power is required to isolate the sensitive analog circuitry from the normal levels
of noise present on the digital power supply.
27.4.8 Dedicated Digital I/O Port Supply Signal
V
DDH
provides 5-V power to the digital I/O functions of QADC port QA and port QB. This
allows those signals to tolerate 5 volts when configured as inputs and drive 5 volts when
configured as outputs.
27.5 Memory Map
The QADC occupies 1 Kbyte, or 512 half-word (16-bit) entries, of address space. Ten
half-word registers are control, port, and status registers, 64 half-word entries are the CCW
table, and 64 half-word entries are the result table which occupies 192 half-word address
locations because the result data is readable in three data alignment formats. Table 27-2 is
the QADC memory map.
Table 27-1. Multiplexed Analog Input Channels
Multiplexed
Analog Input
Channels
ANW Even numbered channels from 0 to 6
ANX Odd numbered channels from 1 to 7
ANY Even numbered channels from 16 to 22
ANZ Odd numbered channels from 17 to 23