Microcontroller User's Manual

MOTOROLA Chapter 26. General Purpose I/O Module 26-13
Memory Map/Register Definition
CLRn register bits are described in Table 26-6.
76543210
Field — CLRn6CLRn5CLRn4CLRn3CLRn2CLRn1CLRn0
Reset 0000_0000
R/W: R R/W
Address IPSBAR + 0x10_0049 (CLRQS)
Figure 26-15. Port Clear Output Data Register (7-bit)
76543210
Field — CLRn5CLRn4CLRn3CLRn2CLRn1CLRn0
Reset 0000_0000
R/W: R R/W
Address IPSBAR + 0x10_0048 (CLRAS), 0x10_004A (CLRSD)
Figure 26-16. Port Clear Output Data Registers (6-bit)
7 43210
Field — CLRn3CLRn2CLRn1CLRn0
Reset 0000_0000
R/W: R R/W
Address IPSBAR + 0x10_004B (CLRTC), 0x10_004C (CLRTD), 0x10_004D (CLRUA)
Figure 26-17. Port Clear Output Data Registers (4-bit)
Table 26-6. CLRn (8-bit,7-bit, 6-bit, and 4-bit) Field Descriptions
Register Bits Name Description
8-bit 7–0 CLRnx Port n clear output data register bits.
1 Never returned for reads; no effect for writes
0 Always returned for reads; clears corresponding PORTn bit
for writes
7-bit 6–0
6-bit 5–0
4-bit 3–0
7-bit 7 — Reserved, should be cleared.
6-bit 7–6
4-bit 7–4