Microcontroller User's Manual

MOTOROLA Chapter 25. FlexCAN 25-31
Programmer’s Model
25.5.10 Interrupt Flag Register (IFLAG)
IFLAG contains one interrupt flag bit per buffer. Each successful transmission/reception
sets the corresponding IFLAG bit and, if the corresponding IMASK bit is set, will generate
an interrupt.
This register contains two 8-bit fields: bits 15-8 (IFLAG_H) and bits 7-0 (IFLAG_L). The
register can be accessed by the master as a 16-bit register, or each byte can be accessed
individually using an 8-bit (byte) access cycle.
Table 25-19 describes the IFLAG fields.
Table 25-18. IMASK Field Descriptions
Bits Name Description
15–0 BUFnM IMASK contains one interrupt mask bit per buffer. It allows the CPU to designate which buffers will
generate interrupts after successful transmission/reception.
0 The interrupt for the corresponding buffer is disabled.
1 The interrupt for the corresponding buffer is enabled.
15 14 13 12 11 10 9 8
Field BUF15I BUF14I BUF13I BUF1I BUF11I BUF10I BUF9I BUF8I
Reset 0000_0000
R/W R/w
76543 0
Field BUF7I BUF6I BUF5I BUF4I BUF3I BUF2I BUF1I BUF0I
Reset 0000_0000
R/W
R/W
Address IPSBAR + 0x1C_0024
Figure 25-15. Interrupt Flag Register (IFLAG)
Table 25-19. IFLAG Field Descriptions
Bits Name Description
15–0 BUFnI IFLAG contains one interrupt flag bit per buffer. Each successful transmission/reception sets the
corresponding IFLAG bit and, if the corresponding IMASK bit is set, an interrupt request will be
generated.
To clear an interrupt flag, first read the flag as a one, and then write it as a zero. Should a new flag
setting event occur between the time that the CPU reads the flag as a one and writes the flag as a
zero, the flag is not cleared. This register can be written to zeros only.
0 The interrupt for the corresponding buffer is disabled.
1 The interrupt for the corresponding buffer is enabled.