Microcontroller User's Manual

25-28 MCF5282 User’s Manual MOTOROLA
Programmer’s Model
25.5.8 FlexCAN Error and Status Register (ESTAT)
ESTAT reflects various error conditions, some general status of the device, and is the source
of three interrupts to the host. The reported error conditions (bits 15:10) are those occurred
since the last time the host read this register. The read action clears these bits to 0.
All the bits in this register are read only, except for BOFF_INT, WAKE_INT and
ERR_INT, which are interrupt sources and can be written by the host to ‘0’.
Section 25.4.12, “Interrupts.”
Table 25-17 describes the ESTAT fields.
Table 25-16. RXGMASK, RX14MASK, and RX15MASK Field Descriptions
Bits Name Description
31–21 MID Mask ID. MID[28:18] are used to mask standard or extended format frames.
0 corresponding incoming ID bit is “don’t care”.
1 corresponding ID bit is checked against the incoming ID bit, to see if a match exists.
20 — Reserved. The IDE bit of a received frame is always compared. Its location in the mask (bit 19) is
always 1, regardless of any CPU write to this bit.
19 — Reserved. The RTR/SRR bit of a received frame is never compared to the corresponding bit in the
MB ID field. Note, however, that remote request frames (RTR = 1) are never received into MBs. RTR
mask bits locations in the mask (bits 20 and 0) are always read as ’0’, regardless of any CPU write
to these bits.
18–1 MID Mask ID. MID[17:0] are only used to mask extended format frames.
0 corresponding incoming ID bit is “don’t care”.
1 corresponding ID bit is checked against the incoming ID bit, to see if a match exists.
0 — Reserved. The RTR/SRR bit of a received frame is never compared to the corresponding bit in the
MB ID field. Note, however, that remote request frames (RTR = 1) are never received into MBs. RTR
mask bits locations in the mask (bits 20 and 0) are always read as ’0’, regardless of any CPU write
to these bits.
15 14 13 12 11 10 9 8
Field BITERR ACKERR CRCERR FORMERR STUFFERR TXWARN RXWARN
Reset 0000_0000
R/W R
76543120
Field IDLE TX/RX FCS — BOFFINT ERRINT WAKEINT
Reset 0000_0000
R/W R
R/W
Address IPSBAR + 0x1C_0020
Figure 25-13. FlexCAN Error and Status Register (ESTAT)