Microcontroller User's Manual

25-24 MCF5282 User’s Manual MOTOROLA
Programmer’s Model
25.5.4 Prescaler Divide Register (PRESDIV)
Table 25-12 describes the PRESDIV fields.
Table 25-11. CANCTRL1 Field Descriptions
Bits Name Description
7 SAMP
Sampling mode. The SAMP bit determines whether the FlexCAN module will sample each received
bit one time or three times to determine its value.
0 One sample, taken at the end of phase buffer segment 1, is used to determine the value of the
received bit.
1 Three samples are used to determine the value of the received bit. The samples are taken at the
normal sample point and at the two preceding periods of the S-clock.
6 — Reserved, should be cleared.
5 TSYNC
Timer synchronize mode. The TSYNC bit enables the mechanism that resets the free-running timer
each time a message is received in Message Buffer 0. This feature provides the means to synchro-
nize multiple FlexCAN stations with a special “SYNC” message (global network time).
0 Timer synchronization disabled.
1 Timer synchronization enabled.
Note: there can be a bit clock skew of four to five counts between different FlexCAN modules that
are using this feature on the same network.
4LBUF
Lowest buffer transmitted first. The LBUF bit defines the transmit-first scheme.
0 Message buffer with lowest ID is transmitted first.
1 Lowest numbered buffer is transmitted first.
3LOM
Listen Only Mode. In this mode the FlexCAN is able to receive messages without giving an acknowl-
edgment or being active on the bus.
0 Regular operation (listen only mode off).
1 Enable listen only mode.
2–0 PROPSEG
Propagation segment time. PROPSEG defines the length of the propagation segment in the bit
time. The valid programmed values are 0 to 7. The propagation segment time is calculated as
follows:
Propagation Segment Time = (PROPSEG + 1) Time Quanta
where
1 Time Quantum = 1 Serial Clock (S-Clock) Period
7 0
Field PRES_DIV
Reset 0000_0000
R/W R/W
Address IPSBAR + 0x1C_0008
Figure 25-9. Prescaler Divide Register (PRESDIV)