Microcontroller User's Manual

MOTOROLA About This Book lv
Revision History
Changed the min value in spec 2 to “4.” Table 33-23/33-25
Changed the min value in spec 3 to “25.” Table 33-23/33-25
Changed the min value in spec 6 to “25.” Table 33-23/33-25
Changed the max value in spec 7 to “30.” Table 33-23/33-25
Changed the max value in spec 8 to “30.” Table 33-23/33-25
Changed the max value in spec 11 to “25.” Table 33-23/33-25
Changed the min value in spec D1 to “5.” Table 33-24/33-27
Changed the min value in spec D2 to “2.” Table 33-24/33-27
Changed offset for the copy of RAMBAR to “0x008.” Table A-3/A-3
2 1/2004 Added MCF5281 device to manual. The MCF5281 implements half the Flash
of the MCF5282.
Throughout Manual
Changed the description of real time debug support. It has only one
user-visible hardware breakpoint register.
1.1/1-1
Change the I field description to read: “Interrupt level mask. Defines the
current interrupt level. Interrupt requests are inhibited for all priority levels
less than or equal to the current level, except the edge-sensitive level 7
request, which cannot be masked.”
Table 2-2/2-6
Replaced the description of PRI1 and PRI2. Table 5-1/5-2
Added note to the SPV bit description, “The BDE bit in the second RAMBAR
register must also be set to allow dual port access to the SRAM. For more
information, see Section 8.4.2, ‘Memory Base Address Register
(RAMBAR).’”
Table 5-1/5-2
Replaced Figure 6-2, “CFM 512K Array Memory Map” and renamed it
“CFM Array Memory Map”
Figure 6-2/6-4
Change value for page erase verify command to 0x06. Table 6-12/6-16
Change value for page erase verify command to 0x06. Table 6-13/6-20
Add the following note to the BDE bit description: “The SPV bit in the CPU’s
RAMBAR must also be set to allow dual port access to the SRAM. For more
information, see Section 5.3.1, ‘SRAM Base Address Register (RAMBAR).’”
Table 8-3/8-5
Remove ÷ 2 from CLKGEN block. Figure 9-1/9-3
Add this text to the end of the first paragraph: “If a specific interrupt request is
completely unused, the ICRnx value can remain in its reset (and disabled)
state.”
10.3.6/10-11
Added the following note: “The wakeup mask level taken from LPICR[6:4] is
adjusted by hardware to allow a level 7 IRQ to generate a wakeup. That is, the
wakeup mask value used by the interrupt controller must be in the range of
0–6.”
10.5/10-17
Changed CSCRn to reflect that AA is set at reset. Figure 12-4/12-8
Removed final paragraph. The paragraph incorrectly states that the MCF5282
does not have a bus monitor.
13.5/13-14
Table iii. Revision History
Revision
Number
Date of
Release
Substantive Changes Section/Page