Microcontroller User's Manual

lii MCF5282 User’s Manual MOTOROLA
Revision History
Revision History
Table iii provides a revision history for this document.
Table iii. Revision History
Revision
Number
Date of
Release
Substantive Changes Section/Page
0 11/2002 Preliminary release.
0.1 1/2003 Changed title from “MCF5282 ColdFire
®
Integrated Microprocessor User’s
Manual” to “MCF5282 ColdFire
®
Microcontroller User’s Manual.”
Title page
Added “This product incorporates SuperFlash® technology licensed from
SST.”
1.1/1-1
Changed equation in footnote to f
sys
= f
ref
× 2(MFD + 2)/2 exp RFD; f
ref
×
2(MFD + 2) ≤ 80 MHz, f
sys
≤ 66 MHz.
Table 9-4/9-6
Multiplied all PLL frequencies in table by 2. Table 9-4/9-6
Changed DTMRx to DTIMx. Figure 10-13/10-12
Changed bit numbers from 63–32 to 31–0. Figure 10-1/10-7
Changed bit numbers from 63–32 to 31–0. Figure 10-3/10-8
Changed bit numbers from 63–32 to 31–0. Figure 10-5/10-9
Added Section 14.2.4, “Chip Configuration Signals.” 14.2.4/14-22
Added Table 14-3. Table 14-3/14-11
Added “Unlike the MCF5272, the MCF5282 does not have an independent
SDRAM clock signal. For the MCF5282, the timing of the SDRAM
controller is controlled by the CLKOUT signal.”
15.2/15-3
Added Section 15.2.3.2, “SDRAM Byte Strobe Connections.” 15.2.3.2/15-13
Added “Note: Because the MCF5282 has 24 external address lines, the
maximum SDRAM address size is 128 Mbits.”
15.2.3.1/15-9
Changed reset value to 0010_0000_0000_0000. Figure 30-4/30-8
Changed “PSTCLK” references to “CLKOUT.” Chapter 29
Changed “TEA
” to “TA.” Figure 29-41/29-46
Changed “RAS0” and “RAS1” to “SDRAM_CS0” and “SDRAM_CS1.” Figure 32-1/32-2
Added Table 32-1. Table 32-1/32-3
Changed max input high voltage to 5.25 V. Table 33-3/33-4
Changed “System Integration Module” to “System Control Module.” Appendix A
1 4/2003 Replaced Figure 6-1 with a more accurate block diagram. Figure 6-1/6-3
Enhanced discussion of Flash blocks. 6.2/6-2
Added “Note:
Enabling Flash security will disable BDM
communications.”
6.3.4.3/6-10
Added “Note:
When Flash security is enabled, the chip will boot in
single chip mode regardless of the external reset configuration.”
6.3.4.3/6-10