Microcontroller User's Manual

23-4 MCF5282 User’s Manual MOTOROLA
Register Descriptions
NOTE
UART registers are accessible only as bytes.
NOTE
Interrupt can mean either an interrupt request asserted to the
CPU or a DMA request.
23.3.1 UART Mode Registers 1 (UMR1n)
The UMR1n registers control configuration. UMR1n can be read or written when the mode
register pointer points to it, at RESET or after a
RESET MODE REGISTER POINTER command
using UCRn[MISC]. After UMR1n is read or written, the pointer points to UMR2n.
0x23C 0x27C 0x2BC (Read) Do not access
2
—
(Write) UART output port bit reset command
registers—(UOP0n
3
) [p. 23-15]
—
1
UMR1n, UMR2n, and UCSRn should be changed only after the receiver/transmitter is issued a software reset command. That is,
if channel operation is not disabled, undesirable results may occur.
2
This address is for factory testing. Reading this location results in undesired effects and possible incorrect transmission or
reception of characters. Register contents may also be changed.
3
Address-triggered commands
7 6 543210
Field RxRTS RxIRQ/FFULL ERR PM PT B/C
Reset 0000_0000
R/W R/W
Address IPSBAR + 0x200 (UART0), 0x240 (UART1), 0x280 (UART2). After UMR1n is read or written, the pointer points to
UMR2n.
Figure 23-2. UART Mode Registers 1 (UMR1n)
Table 23-1. UART Module Memory Map (continued)
IPSBAR Offset
[31:24] [23:16] [15:8] [7:0]
UART0 UART1 UART2