Microcontroller User's Manual

MOTOROLA Chapter 22. Queued Serial Peripheral Interface (QSPI) Module 22-9

Programming Model

In wraparound mode, the QSPI cycles through the queue continuously, even while

requesting interrupt service. QDLYR[SPE] is not cleared when the last command in the

queue is executed. New receive data overwrites previously received data in the receive

RAM. Each time the end of the queue is reached, QIR[SPIFE] is set. QIR[SPIF] is not

automatically reset. If interrupt driven QSPI service is used, the service routine must clear

QIR[SPIF] to abort the current request. Additional interrupt requests during servicing can

be prevented by clearing QIR[SPIFE].

There are two recommended methods of exiting wraparound mode: clearing QWR[WREN]

or setting QWR[HALT]. Exiting wraparound mode by clearing QDLYR[SPE] is not

recommended because this may abort a serial transfer in progress. The QSPI sets SPIF,

clears QDLYR[SPE], and stops the first time it reaches the end of the queue after

QWR[WREN] is cleared. After QWR[HALT] is set, the QSPI finishes the current transfer,

then stops executing commands. After the QSPI stops, QDLYR[SPE] can be cleared.

22.5 Programming Model

Table 22-3 is the QSPI register memory map. Reading reserved locations returns zeros.

The programming model for the QSPI consists of six registers. They are the QSPI mode

There are a total of 80 bytes of memory used for transmit, receive, and control data. This

memory is accessed indirectly using QAR and QDR.

Registers and RAM are written and read by the CPU.

Table 22-3. QSPI Registers

IPSBAR

Offset

[31:24] [23:16] [15:8] [7:0]

0x340 QSPI Mode Register (QMR) [p. 22-10] Reserved

Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these reserved