Microcontroller User's Manual

MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) 20-11
Memory Map and Registers
20.5.11 GPT System Control Register 2 (GPTSCR2)
Table 20-13. GPTIE Field Descriptions
Bit(s) Name Description
7–4 — Reserved, should be cleared.
3–0 CnI Channel interrupt enable. Enables the C[3:0]F flags in GPT flag register 1 to generate
interrupt requests for each channel. These bits are read anytime, write anytime.
1 Corresponding channel interrupt requests enabled
0 Corresponding channel interrupt requests disabled
7 65432 0
Field TOI — PUPT RDPT TCRE PR
Reset 0000_0000
R/W R/W
Address IPSBAR + 0x1A_000D, 0x1B_000D
Figure 20-13. GPT System Control Register 2 (GPTSCR2)
Table 20-14. GPTSCR2 Field Descriptions
Bit(s) Name Description
7 TOI Enables timer overflow interrupt requests.
1 Overflow interrupt requests enabled
0 Overflow interrupt requests disabled
6 — Reserved, should be cleared.
5 PUPT Enables pull-up resistors on the GPT ports when the ports are configured as inputs.
1 Pull-up resistors enabled
0 Pull-up resistors disabled
4 RDPT GPT drive reduction. Reduces the output driver size.
1 Output drive reduction enabled
0 Output drive reduction disabled
3 TCRE Enables a counter reset after a channel 3 compare.
1 Counter reset enabled
0 Counter reset disabled
Note: When the GPT channel 3 registers contain 0x0000 and TCRE is set, the GPT
counter registers remain at 0x0000 all the time. When the GPT channel 3 registers
contain 0xFFFF and TCRE is set, TOF does not get set even though the GPT counter
registers go from 0xFFFF to 0x0000.
2–0 PRn Prescaler bits. Select the prescaler divisor for the GPT counter.
000 Prescaler divisor 1
001 Prescaler divisor 2
010 Prescaler divisor 4
011 Prescaler divisor 8
100 Prescaler divisor 16
101 Prescaler divisor 32
110 Prescaler divisor 64
111 Prescaler divisor 128
Note: The newly selected prescaled clock does not take effect until the next
synchronized edge of the prescaled clock when the clock count transitions to 0x0000.)