Microcontroller User's Manual

MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) 20-9
Memory Map and Registers
Figure 20-8. Fast Clear Flag Logic
20.5.7 GPT Toggle-On-Overflow Register (GPTTOV)
20.5.8 GPT Control Register 1 (GPTCTL1)
7 6543 0
Field — TOV
Reset 0000_0000
R/W R/W
Address IPSBAR + 0x1A_0008, 0x1B_0008
Figure 20-9. GPT Toggle-On-Overflow Register (GPTTOV)
Table 20-10. GPTTOV Field Description
Bit(s) Name Description
7–4 — Reserved, should be cleared.
3–0 TOV Toggles the output compare pin on overflow for each channel. This feature only takes
effect when in output compare mode. When set, it takes precedence over forced output
compare but not channel 3 override events. These bits are read anytime, write
anytime.
1 Toggle output compare pin on overflow feature enabled
0 Toggle output compare pin on overflow feature disabled
7 654321 0
Field OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0
Reset 0000_0000
R/W R/W
Address IPSBAR + 0x1A_0009, 0x1B_0009
Figure 20-10. GPT Control Register 1 (GPTCTL1)
Clear
Write GPTCn Registers
Read GPTCn Registers
TFFCA
Data Bit n
Write GPTFLG1 Register
CnF
CnF Flag