Microcontroller User's Manual

MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB) 20-5

Memory Map and Registers

20.5.1 GPT Input Capture/Output Compare

Select Register (GPTIOS)

0x1A_0010 0x1B_0010 GPT Channel 0 Register High (GPTC0H) S

0x1A_0011 0x1Bb_0011 GPT Channel 0 Register Low (GPTC0L) S

0x1A_0012 0x1B_0012 GPT Channel 1 Register High (GPTC1H) S

0x1A_0013 0x1B_0013 GPT Channel 1 Register Low (GPTC1L) S

0x1A_0014 0x1B_0014 GPT Channel 2 Register High (GPTC2H) S

0x1A_0015 0x1B_0015 GPT Channel 2 Register Low (GPTC2L) S

0x1A_0016 0x1B_0016 GPT Channel 3 Register High (GPTC3H) S

0x1A_0017 0x1B_0017 GPT Channel 3 Register Low (GPTC3L) S

0x1A_0018 0x1B_0018 Pulse Accumulator Control Register (GPTPACTL) S

0x1A_0019 0x1B_0019 Pulse Accumulator Flag Register (GPTPAFLG) S

0x1A_001A 0x1B_001A Pulse Accumulator Counter Register High (GPTPACNTH) S

0x1A_001B 0x1B_001B Pulse Accumulator Counter Register Low (GPTPACNTL) S

0x1A_001C 0x1B_001C Reserved

(2)

—

0x1A_001D 0x1B_001D GPT Port Data Register (GPTPORT) S

0x1A_001E 0x1B_001E GPT Port Data Direction Register (GPTDDR) S

0x1A_001F 0x1B_001F GPT Test Register (GPTTST) S

S = CPU supervisor mode access only.

Writes have no effect, reads return 0s, and the access terminates without a transfer error exception.

7430

Field — IOS

Reset 0000_0000

R/W R/W

Address IPSBAR + 0x401A_0000, 0x401B_0000

Figure 20-2. GPT Input Capture/Output Compare Select Register (GPTIOS)

Table 20-3. GPT Modules Memory Map (continued)

IPSBAR Offset

Bits 7–0 Access

GPTA GPTB