Microcontroller User's Manual

20-4 MCF5282 User’s Manual MOTOROLA
Memory Map and Registers
20.4.2 GPTn3
The GPTn3 pin is for channel 3 input capture and output compare functions or for the pulse
accumulator input. This pin is available for general-purpose I/O when not configured for
timer functions.
20.4.3 SYNCn
The SYNCn pin is for synchronization of the timer counter. It can be used to synchronize
the counter with externally-timed or clocked events. A high signal on this pin clears the
counter.
20.5 Memory Map and Registers
See Table 20-3 for a memory map of the two GPT modules. GPTA has a base address of
IPSBAR + 0x1A_0000. GPTB has a base address of IPSBAR + 0x1B_0000.
NOTE
Reading reserved or unimplemented locations returns zeroes.
Writing to reserved or unimplemented locations has no effect.
Table 20-3. GPT Modules Memory Map
IPSBAR Offset
Bits 7–0 Access
1
GPTA GPTB
0x1A_0000 0x1B_0000 GPT IC/OC Select Register (GPTIOS) S
0x1A_0001 0x1B_0001 GPT Compare Force Register (GPTCFORC) S
0x1A_0002 0x1B_0002 GPT Output Compare 3 Mask Register (GPTOC3M) S
0x1A_0003 0x1B_0003 GPT Output Compare 3 Data Register (GPTOC3D) S
0x1A_0004 0x1B_0004 GPT Counter Register (GPTCNT) S
0x1A_0006 0x1B_0006 GPT System Control Register 1 (GPTSCR1) S
0x1A_0007 0x1B_0007 Reserved
2
—
0x1A_0008 0x1B_0008 GPT Toggle-on-Overflow Register (GPTTOV) S
0x1A_0009 0x1B_0009 GPT Control Register 1 (GPTCTL1) S
0x1A_000A 0x1B_000a Reserved
(2)
—
0x1A_000B 0x1B_000b GPT Control Register 2 (GPTCTL2) S
0x1A_000C 0x1B_000c GPT Interrupt Enable Register (GPTIE) S
0x1A_000D 0x1B_000d GPT System Control Register 2 (GPTSCR2) S
0x1A_000E 0x1B_000e GPT Flag Register 1 (GPTFLG1) S
0x1A_000F 0x1B_000f GPT Flag Register 2 (GPTFLG2) S