Microcontroller User's Manual

19-4 MCF5282 User’s Manual MOTOROLA
Memory Map and Registers
19.5.2.1 PIT Control and Status Register (PCSR)
15 12 11 10 9 8
Field — PRE3 PRE2 PRE1 PRE0
Reset 0000_0000
R/W R R/W
765 4 3210
Field — DOZE HALTED OVW PIE PIF RLD EN
Reset 0000_0000
R/W R R/W
Address IPSBAR + 0x0015_0000 and 0x0015_0001 (PIT0); 0x0016_0000 and 0x0016_0001 (PIT1); 0x0017_0000
and 0x0017_0001 (PIT2); 0x0018_0000 and 0x0018_0001 (PIT3)
Figure 19-2. PIT Control and Status Register (PCSR)
Table 19-3. PCSR Field Descriptions
Bit(s) Name Description
15–12 — Reserved, should be cleared.
11–8 PRE Prescaler. The read/write prescaler bits select the system clock divisor to generate the PIT
clock. To accurately predict the timing of the next count, change the PRE[3:0] bits only when
the enable bit (EN) is clear. Changing the PRE[3:0] resets the prescaler counter. System reset
and the loading of a new value into the counter also reset the prescaler counter. Setting the EN
bit and writing to PRE[3:0] can be done in this same write cycle. Clearing the EN bit stops the
prescaler counter.
7—Reserved.
PRE System Clock Divisor PRE System Clock Divisor
0000 2 1000 512
0001 4 1001 1,024
0010 8 1010 2,048
0011 16 1011 4,096
0100 32 1100 8,192
0101 64 1101 16,384
0110 128 1110 32,768
0111 256 1111 65,536