Microcontroller User's Manual

MOTOROLA Chapter 18. Watchdog Timer Module 18-3
Memory Map and Registers
18.5.2 Registers
The watchdog timer programming model consists of these registers:
• Watchdog control register (WCR), which configures watchdog timer operation
• Watchdog modulus register (WMR), which determines the timer modulus
reload value
• Watchdog count register (WCNTR), which provides visibility to the watchdog
counter value
• Watchdog service register (WSR), which requires a service sequence to
prevent reset
18.5.2.1 Watchdog Control Register (WCR)
The 16-bit WCR configures watchdog timer operation.
Table 18-2. Watchdog Timer Module Memory Map
IPSBAR Offset Bits 15–8 Bits 7–0 Access
1
1
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses
to supervisor only addresses have no effect and result in a cycle termination transfer error.
0x0014_0000 Watchdog Control Register (WCR) S
0x0014_0002 Watchdog Modulus Register (WMR) S
0x0014_0004 Watchdog Count Register (WCNTR) S/U
0x0014_0006 Watchdog Service Register (WSR) S/U
15 14 13 12 11 10 9 8
Field —
Reset 0000_0000
R/W R
765 4 3210
Field — WAIT DOZE HALTED EN
Reset 0000_1111
R/W R R/W
Address IPSBAR + 0x0014_0000, 0x0014_0001
Figure 18-2. Watchdog Control Register (WCR)