Microcontroller User's Manual

MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-39
Programming Model
17.5.4.16 Descriptor Group Upper Address (GAUR)
The GAUR is written by the user. This register contains the upper 32 bits of the 64-bit hash
table used in the address recognition process for receive frames with a multicast address.
This register must be initialized by the user.
17.5.4.17 Descriptor Group Lower Address (GALR)
The GALR register is written by the user. This register contains the lower 32 bits of the
64-bit hash table used in the address recognition process for receive frames with a multicast
address. This register must be initialized by the user.
Table 17-27. IALR Field Descriptions
Bits Name Description
31–0 IADDR2 The lower 32 bits of the 64-bit hash table used in the address
recognition process for receive frames with a unicast
address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0
of IADDR2 contains hash index bit 0.
31 16
Field GADDR1
Reset Uninitialized
R/W R/W
15 0
Field GADDR1
Reset Uninitialized
R/W R/W
Address IPSBAR + 0x1120
Figure 17-19. Descriptor Group Upper Address Register (GAUR)
Table 17-28. GAUR Field Descriptions
Bits Name Description
31–0 GADDR1 The GADDR1 register contains the upper 32 bits of the 64-bit
hash table used in the address recognition process for
receive frames with a multicast address. Bit 31 of GADDR1
contains hash index bit 63. Bit 0 of GADDR1 contains hash
index bit 32.