Microcontroller User's Manual

MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-37
Programming Model
17.5.4.13 Opcode/Pause Duration Register (OPD)
The OPD is read/write accessible. This register contains the 16-bit opcode and 16-bit pause
duration fields used in transmission of a PAUSE frame. The opcode field is a constant
value, 0x0001. When another node detects a PAUSE frame, that node will pause
transmission for the duration specified in the pause duration field. This register is not reset
and must be initialized by the user.
17.5.4.14 Descriptor Individual Upper Address Register (IAUR)
The IAUR is written by the user. This register contains the upper 32 bits of the 64-bit
individual address hash table used in the address recognition process to check for possible
match with the DA field of receive frames with an individual DA. This register is not reset
and must be initialized by the user.
Table 17-24. PAUR Field Descriptions
BIts Name Description
31–16 PADDR2 Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual
address to be used for exact match, and the Source Address
field in PAUSE frames.
15–0 TYPE Type field in PAUSE frames. These 16-bits are a constant
value of 0x8808.
31 16
Field OPCODE
Reset 0000_0000_0000_0001
R/W R
15 0
Field PAUSE_DUR
Reset Uninitialized
R/W R/W
Address IPSBAR + 0x10EC
Figure 17-16. Opcode/Pause Duration Register (OPD)
Table 17-25. OPD Field Descriptions
Bits Name Description
31–16 OPCODE Opcode field used in PAUSE frames.
These bits are a constant, 0x0001.
15–0 PAUSE_DUR Pause Duration field used in PAUSE frames.