Microcontroller User's Manual

17-32 MCF5282 User’s Manual MOTOROLA
Programming Model
If the system clock is 25 MHz, programming this register to 0x0000_0005 will result in an
EMDC frequency of 25 MHz * 1/10 = 2.5 MHz. A table showing optimum values for
MII_SPEED as a function of system clock frequency is provided below.
17.5.4.8 MIB Control Register (MIBC)
The MIBC is a read/write register used to provide control of and to observe the state of the
MIB block. This register is accessed by user software if there is a need to disable the MIB
block operation. For example, in order to clear all MIB counters in RAM the user should
disable the MIB block, then clear all the MIB RAM locations, then enable the MIB block.
The MIB_DISABLE bit is reset to 1. See Table 17-11 for the locations of the MIB counters.
Table 17-19. Programming Examples for MSCR
System Clock Frequency MII_SPEED (field in reg) EMDC frequency
25 MHz 0x5 2.5 MHz
33 MHz 0x7 2.36 MHz
40 MHz 0x8 2.5 MHz
50 MHz 0xA 2.5 MHz
66 MHz 0xD 2.5 MHz
31 30 16
Field MIB_DISABLE MIB_IDLE —
Reset 1100_0000_000_000
R/W R/W
15 0
Field —
Reset 0000_0000_0000_0000
R/W R/W
Address IPSBAR + 0x1064
Figure 17-11. MIB Control Register (MIBC)
Table 17-20. MIBC Field Descriptions
Bits Name Description
31 MIB_DISABLE A read/write control bit. If set, the MIB logic will halt and not update
any MIB counters.
30 MIB_IDLE A read-only status bit. If set the MIB block is not currently updating
any MIB counters.
29–0 — Reserved.