Microcontroller User's Manual

MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-23
Programming Model
17.5.4 Registers
The following sections describe each register in detail.
17.5.4.1 Ethernet Interrupt Event Register (EIR)
When an event occurs that sets a bit in the EIR, an interrupt will be generated if the
corresponding bit in the interrupt mask register (EIMR) is also set. The bit in the EIR is
cleared if a one is written to that bit position; writing zero has no effect. This register is
cleared upon hardware reset.
These interrupts can be divided into operational interrupts, transceiver/network error
interrupts, and internal error interrupts. Interrupts which may occur in normal operation are
GRA, TXF, TXB, RXF, RXB, and MII. Interrupts resulting from errors/problems detected
0x1290 RMON_R_CRC_ALIGN RMON Rx Packets w CRC/Align error
0x1294 RMON_R_UNDERSIZE RMON Rx Packets < 64 bytes, good crc
0x1298 RMON_R_OVERSIZE RMON Rx Packets > MAX_FL bytes, good crc
0x129C RMON_R_FRAG RMON Rx Packets < 64 bytes, bad crc
0x12A0 RMON_R_JAB RMON Rx Packets > MAX_FL bytes, bad crc
0x12A4 RMON_R_RESVD_0
0x12A8 RMON_R_P64 RMON Rx 64 byte packets
0x12AC RMON_R_P65TO127 RMON Rx 65 to 127 byte packets
0x12B0 RMON_R_P128TO255 RMON Rx 128 to 255 byte packets
0x12B4 RMON_R_P256TO511 RMON Rx 256 to 511 byte packets
0x12B8 RMON_R_P512TO1023 RMON Rx 512 to 1023 byte packets
0x12BC RMON_R_P1024TO2047 RMON Rx 1024 to 2047 byte packets
0x12C0 RMON_R_P_GTE2048 RMON Rx packets w > 2048 bytes
0x12C4 RMON_R_OCTETS RMON Rx Octets
0x12C8 IEEE_R_DROP Count of frames not counted correctly
0x12CC IEEE_R_FRAME_OK Frames Received OK
0x12D0 IEEE_R_CRC Frames Received with CRC Error
0x12D4 IEEE_R_ALIGN Frames Received with Alignment Error
0x12D8 IEEE_R_MACERR Receive Fifo Overflow count
0x12DC IEEE_R_FDXFC Flow Control Pause frames received
0x12E0 IEEE_R_OCTETS_OK Octet count for Frames Rcvd w/o Error
Table 17-11. MIB Counters Memory Map (continued)
IPSBAR
Offset
Mnemonic Description