Microcontroller User's Manual

MOTOROLA Chapter 17. Fast Ethernet Controller (FEC) 17-21
Programming Model
17.5.3 MIB Block Counters Memory Map
Table 17-11 defines the MIB Counters memory map which defines the locations in the MIB
RAM space where hardware maintained counters reside. These fall in the 0x1200-0x13FF
address offset range. The counters are divided into two groups.
RMON counters are included which cover the Ethernet Statistics counters defined in RFC
1757. In addition to the counters defined in the Ethernet Statistics group, a counter is
included to count truncated frames as the FEC only supports frame lengths up to 2047
bytes. The RMON counters are implemented independently for transmit and receive to
insure accurate network statistics when operating in full duplex mode.
IEEE counters are included which support the Mandatory and Recommended counter
packages defined in section 5 of ANSI/IEEE Std. 802.3 (1998 edition). The IEEE Basic
Package objects are supported by the FEC but do not require counters in the MIB block. In
addition, some of the recommended package objects which are supported do not require
MIB counters. Counters for transmit and receive full duplex flow control frames are
included as well.
0x1084 RCR 32 Receive Control Register
0x10C4 TCR 32 Transmit Control Register
0x10E4 PALR 32 Physical Address Low Register
0x10E8 PAUR 32 Physical Address High+ Type Field
0x10EC OPD 32 Opcode + Pause Duration
0x1118 IAUR 32 Upper 32 bits of Individual Hash Table
0x111C IALR 32 Lower 32 Bits of Individual Hash Table
0x1120 GAUR 32 Upper 32 bits of Group Hash Table
0x1124 GALR 32 Lower 32 bits of Group Hash Table
0x1144 TFWR 32 Transmit FIFO Watermark
0x114C FRBR 32 FIFO Receive Bound Register
0x1150 FRSR 32 FIFO Receive FIFO Start Registers
0x1180 ERDSR 32 Pointer to Receive Descriptor Ring
0x1184 ETDSR 32 Pointer to Transmit Descriptor Ring
0x1188 EMRBR 32 Maximum Receive Buffer Size
Table 17-10. FEC Register Memory Map (continued)
IPSBAR
Offset
Name Width Description