Microcontroller User's Manual

MOTOROLA Tabl es xxxv
TABLES
Table
Number
Title
Page
Number
10-2 Interrupt Controller Base Addresses........................................................................... 10-5
10-3 Interrupt Controller Memory Map.............................................................................. 10-5
10-4 IPRHn Field Descriptions........................................................................................... 10-7
10-5 IPRLn Field Descriptions ........................................................................................... 10-7
10-6 IMRHn Field Descriptions.......................................................................................... 10-8
10-8 INTFRCHn Field Descriptions................................................................................... 10-9
10-7 IMRLn Field Descriptions .......................................................................................... 10-9
10-9 INTFRCLn Field Descriptions ................................................................................. 10-10
10-10 IRQn Field Descriptions ........................................................................................... 10-10
10-11 IACKLPRn Field Descriptions................................................................................. 10-11
10-12 ICRnx Field Descriptions ......................................................................................... 10-12
10-13 Interrupt Source Assignment for INTC0 .................................................................. 10-12
10-14 Interrupt Source Assignment for INTC1 .................................................................. 10-15
10-15 SWIACK and L1IACK-L7IACK Field Descriptions............................................... 10-16
11-1 Edge Port Module Operation in Low-power Modes .................................................. 11-2
11-2 Edge Port Module Memory Map ................................................................................ 11-3
11-3 EPPAR Field Descriptions.......................................................................................... 11-4
11-4 EPDD Field Descriptions............................................................................................ 11-5
11-5 EPIER Field Descriptions........................................................................................... 11-5
11-6 EPDR Field Descriptions............................................................................................ 11-6
11-7 EPPDR Field Descriptions.......................................................................................... 11-6
11-8 EPFR Field Descriptions ............................................................................................ 11-7
12-1 Chip Select Module Signals........................................................................................ 12-1
12-2 Byte Enables/Byte Write Enable Signal Settings ....................................................... 12-2
12-3 Accesses by Matches in CSARs and DACRs............................................................. 12-4
12-4 D[19:18] External Boot Chip Select Configuration ................................................... 12-5
12-5 Chip Select Registers .................................................................................................. 12-5
12-6 CSARn Field Description ........................................................................................... 12-7
12-7 CSMRn Field Descriptions......................................................................................... 12-7
12-8 CSCRn Field Descriptions.......................................................................................... 12-9
13-1 ColdFire Bus Signal Summary .................................................................................. 13-1
13-2 Accesses by Matches in CSCRs and DACRs............................................................. 13-4
13-3 Bus Cycle States ........................................................................................................ 13-5
13-4 Allowable Line Access Patterns ............................................................................... 13-11
14-1 MCF5282 Signal Description .................................................................................... 14-3
14-2 MCF5282 Alphabetical Signal Index ......................................................................... 14-8
14-3 MCF5282 Signals and Pin Numbers Sorted by Function......................................... 14-11
14-4 Pin Reset States at Reset (Single-Chip Mode).......................................................... 14-17
14-5 Default Signal Functions After System Reset (External Boot Mode) ...................... 14-17
14-6 Transfer Size Encoding............................................................................................. 14-20
14-7 Processor Status Encoding........................................................................................ 14-32
15-1 SDRAM Commands ................................................................................................... 15-3
15-2 Synchronous DRAM Signal Connections .................................................................. 15-4