Microcontroller User's Manual

MOTOROLA Chapter 15. Synchronous DRAM Controller Module 15-19
SDRAM Example
Figure 15-10. Mode Register Set (MRS) Command
15.3 SDRAM Example
This example interfaces a 512K x 32-bit x 4 bank SDRAM component to a MCF5282
operating at 40 MHz. Table 15-25 lists design specifications for this example.
Table 15-25. SDRAM Example Specifications
Parameter Specification
Speed grade (-8E) 40 MHz (25-ns period)
10 rows, 8 columns
Two bank-select lines to access four internal banks
ACTV-to-read/write delay (t
RCD
) 20 ns (min.)
Period between auto-refresh and ACTV command (t
RC
) 70 ns
ACTV command to precharge command (t
RAS
) 48 ns (min.)
Precharge command to
ACTV command (t
RP
) 20 ns (min.)
Last data input to PALL command (t
RWL
) 1 bus clock (25 ns)
Auto-refresh period for 4096 rows (t
REF
)64 mS
A[31:0]
SRAS
, SCAS
DRAMW
D[31:0]
MRS
SD_CS[1] or [0]
CLKOUT