Microcontroller User's Manual

MOTOROLA Chapter 15. Synchronous DRAM Controller Module 15-13
SDRAM Controller Operation
15.2.3.2 SDRAM Byte Strobe Connections
Figure 15-5 shows SDRAM connections for port sizes of 32, 16, or 8 bits.
Figure 15-5. Connections for External Memory Port Sizes
15.2.3.3 Interfacing Example
The tables in the previous section can be used to configure the interface in the following
example. To interface one 2M x 32-bit x 4 bank SDRAM component (8 columns) to the
MCF5282, the connections shown in Table 15-24 would be used.
15.2.3.4 Burst Page Mode
SDRAM can efficiently provide data when an SDRAM page is opened. As soon as SCAS
is issued, the SDRAM accepts a new address and asserts SCAS every CLKOUT for as long
as accesses occur in that page. In burst page mode, there are multiple read or write
operations for every
ACTV command in the SDRAM if the requested transfer size exceeds
Table 15-23. MCF5282 to SDRAM Interface (32-Bit Port, 12-Column Address Lines)
MCF5282
Pins
A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A23
Row 15 14 13 12 11 10 9 17 19 21 23
Column 2 3 4 5 6 7 8 16 18 20 22
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
Table 15-24. SDRAM Hardware Connections
SDRAM
Pins
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 = CMD BA0 BA1
MCF5282
Pins
A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22
Processor
Data Bus
Byte 0
8-Bit Port
16-Bit Port
32-Bit Port
Byte 1
Byte 2
Byte 3
Byte 0 Byte 1
Byte 2 Byte 3
Byte 0 Byte 1 Byte 2 Byte 3
D[31:24] D[23:16] D[15:8] D[7:0]
External
Memory
Memory
Memory
Byte Enable BS3
BS2 BS1 BS0
Driven with
indeterminate values
Driven with
indeterminate values