Microcontroller User's Manual

14-10 MCF5282 User’s Manual MOTOROLA
Overview
QADC analog supply Supplies positive power to the ESD structures in the QADC
pads.
I
QSPI_CLK Provides the serial clock from the QSPI. O
QSPI_CS[3:0] Provide QSPI peripheral chip selects. O
QSPI_DIN Provides serial data to the QSPI. I
QSPI_DOUT Provides serial data from the QSPI. O
R/W Indicates the direction of the data transfer on the bus. I/O
RCON Reset configuration select. I
RSTI Asserted to enter reset exception processing. I
RSTO Automatically asserted with RSTI. Negation indicates that the
PLL has regained its lock.
O
SCAS
SDRAM synchronous column address strobe. O
SCKE SDRAM clock enable. O
SCL Clock signal for the I
2
C interface. I/O
SDA Data input/output for the I
2
C interface. I/O
SDRAM_CS[1:0] Interface to the chip-select lines of the SDRAMs within a
memory block.
O
SIZ[1:0] Specify the data access size of the current external bus
reference.
O
SRAS SDRAM synchronous row address strobe. O
VSTBY Provides standby voltage to RAM array if VDD is lost. I
SYNCA/SYNCB Clear the timer’s clock, providing a means of synchronization
to externally clocked or timed events.
I
TA
Indicates that the external data transfer is complete and should
be asserted for one CLKOUT cycle.
I
TEA
Indicates that an error condition exists for the bus transfer. I
TEST Reserved, should be connected to VSS. I
TCK JTAG test logic clock. I
TIP
Asserted to indicate that a bus transfer is in progress. Negated
during idle bus cycles.
O
TS
Asserted during the first CLKOUT cycle of a transfer when
address and attributes are valid.
O
UCTS
[1:0] Signals UART that it can begin data transmission. I
URTS
[1:0] Automatic UART request to send outputs. O
URXD[2:0] Receiver serial data inputs. I
Table 14-2. MCF5282 Alphabetical Signal Index (Continued)
Abbreviation Function I/O