Microcontroller User's Manual

ILLUSTRATIONS
Figure
Number
Title
Page
Number
MOTOROLA Illustrations xxix
25-15 Interrupt Flag Register (IFLAG)............................................................................... 25-31
25-16 FlexCAN Receive Error Counter (RXECTR) .......................................................... 25-32
25-17 FlexCAN Transmit Error Counter (TXECTR)......................................................... 25-32
26-1 MCF5282 Ports Module Block Diagram.................................................................... 26-2
26-2 Port Output Data Registers (8-bit) .............................................................................. 26-8
26-3 Port Output Data Register (7-bit)................................................................................ 26-8
26-4 Port Output Data Registers (6-bit) .............................................................................. 26-8
26-5 Port Output Data Registers (4-bit) .............................................................................. 26-9
26-6 Port Data Direction Registers (8-bit) .......................................................................... 26-9
26-7 Port Data Direction Register (7-bit).......................................................................... 26-10
26-8 Port Data Direction Registers (6-bit) ........................................................................ 26-10
26-9 Port Data Direction Registers (4-bit) ........................................................................ 26-10
26-10 Port Pin Data/Set Data Registers (8-bit) .................................................................. 26-11
26-11 Port Pin Data/Set Data Register (7-bit)..................................................................... 26-11
26-12 Port Pin Data/Set Data Registers (6-bit) ................................................................... 26-11
26-13 Port Pin Data/Set Data Registers (4-bit) ................................................................... 26-12
26-14 Port Clear Output Data Registers (8-bit) .................................................................. 26-12
26-15 Port Clear Output Data Register (7-bit).................................................................... 26-13
26-16 Port Clear Output Data Registers (6-bit) .................................................................. 26-13
26-17 Port Clear Output Data Registers (4-bit) .................................................................. 26-13
26-18 Port B/C/D Pin Assignment Register (PBCDPAR).................................................. 26-14
26-19 Port E Pin Assignment Register (PEPAR) ............................................................... 26-15
26-20 Port F Pin Assignment Register (PFPAR)................................................................ 26-17
26-21 Port J Pin Assignment Register (PJPAR) ................................................................ 26-18
26-22 Port SD Pin Assignment Register (PSDPAR) .......................................................... 26-19
26-23 Port AS Pin Assignment Register (PASPAR) .......................................................... 26-19
26-24 Port EH/EL Pin Assignment Register (PEHLPAR) ................................................ 26-20
26-25 Port QS Pin Assignment Register (PQSPAR) .......................................................... 26-21
26-26 Port TC Pin Assignment Register (PTCPAR) ......................................................... 26-22
26-27 Port TD Pin Assignment Register (PTDPAR)......................................................... 26-23
26-28 Port UA Pin Assignment Register (PUAPAR)........................................................ 26-24
26-29 Digital Input Timing ................................................................................................. 26-25
26-30 Digital Output Timing .............................................................................................. 26-26
27-1 QADC Block Diagram................................................................................................ 27-2
27-2 QADC Input and Output Signals ................................................................................ 27-5
27-3 QADC Module Configuration Register (QADCMCR) .............................................. 27-9
27-4 QADC Port QA Data Register (PORTQA) .............................................................. 27-10
27-5 QADC Port QB Data Register (PORTQB)............................................................... 27-10
27-6 QADC Port QA Data Direction Register (DDRQA)................................................ 27-11
27-7 Port QB Data Direction Register (DDRQB)............................................................. 27-11
27-8 QADC Control Register 0 (QACR0)........................................................................ 27-12
27-9 QADC Control Register 1 (QACR1)........................................................................ 27-14
27-10 QADC Control Register 2 (QACR2)........................................................................ 27-17