Microcontroller User's Manual

MOTOROLA Chapter 13. External Interface Module (EIM) 13-13
Data Transfer Operation
Figure 13-15. Line Read Burst-Inhibited, Fast Termination, External Termination
13.4.7.3 Line Write Bus Cycles
Figure 13-16 shows a line access write with zero wait states. It begins like a basic write bus
cycle with data driven one clock after TS
. The next pipelined burst data is driven a cycle
after the write data is registered (on the rising edge of S6). Each subsequent burst takes a
single cycle. Note that as with the line read example in Figure 13-12, CS
n remain asserted
throughout the burst transfer. This example shows the behavior of the address lines for both
internal and external termination. Note that when external termination is used, the address
lines change with SIZ[1:0].
Figure 13-16. Line Write Burst (2-1-1-1), Internal/External Termination
A[31:0]
R/W
TIP
SIZ[1:0]
TS
D[31:0]
TA
Line Longword
Basic Fast Fast Fast
A[3:2] = 00 A[3:2] = 01 A[3:2] = 10 A[3:2] = 11
S0 S1 S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S7S6
Read Read
Read Read
CLKOUT
CS
n, BSn, OE
A[31:0]
SIZ[1:0]
TS
CSn, OE, BSn
D[31:0]
TA
WriteWrite Write Write
S0 S1 S2 S3 S4 S5 S10S9S8S7S6 S11
CLKOUT
A[31:0]
Internal Termination
External Termination
R/W
, TIP