Microcontroller User's Manual

MOTOROLA Chapter 13. External Interface Module (EIM) 13-5
Data Transfer Operation
3. The last clock of the bus cycle uses what would be an idle clock between cycles to
provide hold time for address, attributes and write data. Figure 13-6 and Figure 13-8
show the basic read and write operations.
13.4.2 Data Transfer Cycle States
The data transfer operation in the MCF5282 is controlled by an on-chip state machine. Each
bus clock cycle is divided into two states. Even states occur when CLKOUT is high and
odd states occur when CLKOUT is low. The state transition diagram for basic and fast
termination read and write cycles are shown in Figure 13-4.
Figure 13-4. Data Transfer State Transition Diagram
Table 13-3 describes the states as they appear in subsequent timing diagrams.
Table 13-3. Bus Cycle States
State Cycle CLKOUT Description
S0 All High The read or write cycle is initiated in S0. On the rising edge of CLKOUT, the
MCF5282 places a valid address on the address bus and drives R/W
high for a
read and low for a write, if it is not already in the appropriate state. The MCF5282
asserts TIP, SIZ[1:0], and TS on the rising edge of CLKOUT.
S1 All Low The appropriate CS
n, BS, and OE signals assert on the CLKOUT falling edge.
Fast
Termination
TA
must be asserted during S1. Data is made available by the external device
and is sampled on the rising edge of CLKOUT with TA
asserted.
S2 Read/write
(skipped fast
termination)
High TS
is negated on the rising edge of CLKOUT in S2.
Write The data bus is driven out of high impedance as data is placed on the bus on the
rising edge of CLKOUT.
S0
S3
S5
S4
S1
S2
Basic
Next Cycle
Wait
States
Read/Write
Fast
Termination