Microcontroller User's Manual

ILLUSTRATIONS
Figure
Number
Title
Page
Number
xxvi MCF5282 User’s Manual MOTOROLA
17-3 Ethernet Address Recognitionq—Microcode Decisions .......................................... 17-13
17-4 Ethernet Interrupt Event Register (EIR) ................................................................... 17-24
17-5 Interrupt Mask Register (EIMR)............................................................................... 17-26
17-6 Receive Descriptor Active Register (RDAR)........................................................... 17-27
17-7 Transmit Descriptor Active Register (TDAR).......................................................... 17-28
17-8 Ethernet Control Register (ECR)............................................................................. 17-28
17-9 MII Management Frame Register (MMFR) ............................................................. 17-29
17-10 MII Speed Control Register (MSCR) ....................................................................... 17-31
17-11 MIB Control Register (MIBC) ................................................................................. 17-32
17-12 Receive Control Register (RCR) .............................................................................. 17-33
17-13 Transmit Control Register (TCR) ............................................................................. 17-34
17-14 Physical Address Low Register (PALR) .................................................................. 17-36
17-15 Physical Address High Register (PAUR) ................................................................. 17-36
17-16 Opcode/Pause Duration Register (OPD) .................................................................. 17-37
17-17 Descriptor Individual Upper Address Register (IAUR) ........................................... 17-38
17-18 Descriptor Individual Lower Address Register (IALR) ........................................... 17-38
17-19 Descriptor Group Upper Address Register (GAUR)................................................ 17-39
17-20 Descriptor Group Lower Address Register (GALR)................................................ 17-40
17-21 FIFO Transmit FIFO Watermark Register (TFWR)................................................. 17-40
17-22 FIFO Receive Bound Register (FRBR) .................................................................... 17-41
17-23 FIFO Receive Start Register (FRSR)........................................................................ 17-42
17-24 Receive Descriptor Ring Start Register (ERDSR) ................................................... 17-43
17-25 Transmit Buffer Descriptor Ring Start Register (ETDSR)....................................... 17-43
17-26 Receive Buffer Size Register (EMRBR) .................................................................. 17-44
17-27 Receive Buffer Descriptor (RxBD) .......................................................................... 17-47
17-28 Transmit Buffer Descriptor (TxBD) ......................................................................... 17-50
18-1 Watchdog Timer Block Diagram................................................................................ 18-2
18-2 Watchdog Control Register (WCR)............................................................................ 18-3
18-3 Watchdog Modulus Register (WMR)......................................................................... 18-4
18-4 Watchdog Count Register (WCNTR)......................................................................... 18-5
18-5 Watchdog Service Register (WSR) ............................................................................ 18-6
19-1 PIT Block Diagram..................................................................................................... 19-1
19-2 PIT Control and Status Register (PCSR).................................................................... 19-4
19-3 PIT Modulus Register (PMR)..................................................................................... 19-6
19-4 PIT Count Register (PCNTR)..................................................................................... 19-6
19-5 Counter Reloading from the Modulus Latch .............................................................. 19-7
19-6 Counter in Free-Running Mode.................................................................................. 19-7
20-1 GPT Block Diagram ................................................................................................... 20-2
20-2 GPT Input Capture/Output Compare Select Register (GPTIOS) ............................... 20-5
20-3 GPT Input Compare Force Register (GPCFORC) ..................................................... 20-6
20-4 GPT Output Compare 3 Mask Register (GPTOC3M)................................................ 20-6
20-5 GPT Output Compare 3 Data Register (GPTOC3D).................................................. 20-7