Microcontroller User's Manual

12-4 MCF5282 User’s Manual MOTOROLA
Chip Select Operation
12.3.1.1 8-, 16-, and 32-Bit Port Sizing
Static bus sizing is programmable through the port size bits, CSCR[PS]. See
Section 12.4.1.3 for more information. Figure 12-1 shows the correspondence between the
data bus and the external byte strobe control lines (BS
[3:0]). Note that all byte lanes are
driven, although the state of unused byte lanes is undefined.
Figure 12-1. Connections for External Memory Port Sizes
12.3.1.2 External Boot Chip Select Operation
CS0, the external boot chip select, allows address decoding for boot ROM before system
initialization. Its operation differs from other external chip select outputs after system reset.
After system reset, CS0
is asserted for every external access. No other chip select can be
used until the valid bit, CSMR0[V], is set, at which point CS0
functions as configured and
Table 12-3. Accesses by Matches in CSARs and DACRs
Number of CSCR Matches Number of DACR Matches Type of Access
00External
1 0 Defined by CSAR
Multiple 0 External, burst-inhibited, 32-bit
0 1 Defined by DACRs
1 1 Undefined
Multiple 1 Undefined
0 Multiple Undefined
1 Multiple Undefined
Multiple Multiple Undefined
Byte 0
8-bit port
16-bit port
32-bit port
Byte 1
Byte 2
Byte 3
Byte 0 Byte 1
Byte 2 Byte 3
Byte 0 Byte 1 Byte 2 Byte 3
D[31:24] D[23:16] D[15:8] D[7:0]
External
memory
memory
memory
data bus
BS3 BS2 BS1 BS0
Driven, undefined
Driven, undefined