Microcontroller User's Manual

MOTOROLA Chapter 11. Edge Port Module (EPORT) 11-5
Memory Map and Registers
11.4.2.3 Edge Port Interrupt Enable Register (EPIER)
11.4.2.4 Edge Port Data Register (EPDR)
Table 11-4. EPDD Field Descriptions
Bit(s) Name Description
7–1 EPDDx Setting any bit in the EPDDR configures the corresponding pin as an output. Clearing any bit
in EPDDR configures the corresponding pin as an input. Pin direction is independent of the
level/edge detection configuration. Reset clears EPDD7-EPDD1.
To use an EPORT pin as an external interrupt request source, its corresponding bit in EPDDR
must be clear. Software can generate interrupt requests by programming the EPORT data
register when the EPDDR selects output.
1 Corresponding EPORT pin configured as output
0 Corresponding EPORT pin configured as input
0 — Reserved, should be cleared.
765 43210
Field EPIE7 EPIE6 EPIE5 EPIE4 EPIE3 EPIE2 EPIE1 —
Reset 0000_0000
R/W R/W R
Address IPSBAR + 0x0013_0003
Figure 11-4. EPORT Port Interrupt Enable Register (EPIER)
Table 11-5. EPIER Field Descriptions
Bit(s) Name Description
7–1 EPIEx Edge port interrupt enable bits enable EPORT interrupt requests. If a bit in EPIER is set,
EPORT generates an interrupt request when:
• The corresponding bit in the EPORT flag register (EPFR) is set or later becomes set.
• The corresponding pin level is low and the pin is configured for level-sensitive operation.
Clearing a bit in EPIER negates any interrupt request from the corresponding EPORT pin.
Reset clears EPIE7-EPIE1.
1 Interrupt requests from corresponding EPORT pin enabled
0 Interrupt requests from corresponding EPORT pin disabled
0 — Reserved, should be cleared.
765 43210
Field EPD7 EPD6 EPD5 EPD4 EPD3 EPD2 EPD1 —
Reset 1111_1111
R/W R/W R
Address IPSBAR + 0x0013_0004
Figure 11-5. EPORT Port Data Register (EPDR)