Microcontroller User's Manual

MOTOROLA Chapter 10. Interrupt Controller Modules 10-5
Memory Map
10.2 Memory Map
The register programming model for the interrupt controllers is memory-mapped to a
256-byte space. In the following discussion, there are a number of program-visible registers
greater than 32 bits in size. For these control fields, the physical register is partitioned into
two 32-bit values: a register “high” (the upper longword) and a register “low” (the lower
longword). The nomenclature <reg_name>H and <reg_name>L is used to reference these
values.
The registers and their locations are defined in Table 10-3. The offsets listed start from the
base address for each interrupt controller. The base addresses for the interrupt controllers
are listed below:
Table 10-2. Interrupt Controller Base Addresses
Interrupt Controller Number Base Address
INTC0 IPSBAR + 0xC00
INTC1 IPSBAR + 0xD00
Global IACK Registers Space
1
1
This address space only contains the SWIACK and L1ACK-L7IACK registers. See Section 10.3.7, “Software
and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)" for more information
IPSBAR + 0xF00
Table 10-3. Interrupt Controller Memory Map
Module Offset Bits[31:24] Bits[23:16] Bits[15:8] Bits[7:0]
0x00 Interrupt Pending Register High (IPRH), [63:32]
0x04 Interrupt Pending Register Low (IPRL), [31:1]
0x08 Interrupt Mask Register High (IMRH), [63:32]
0x0c Interrupt Mask Register Low (IMRL), [31:0]
0x10 Interrupt Force Register High (INTFRCH), [63:32]
0x14 Interrupt Force Register Low (INTFRCL), [31:1]
0x18 IRLR[7:1] IACKLPR[7:0] Reserved
0x1c - 0x3c Reserved
0x40 Reserved ICR01 ICR02 ICR03
0x44 ICR04 ICR05 ICR06 ICR07
0x48 ICR08 ICR09 ICR10 ICR11
0x4c ICR12 ICR13 ICR14 ICR15
0x50 ICR16 ICR17 ICR18 ICR19
0x54 ICR20 ICR21 ICR22 ICR23
0x58 ICR24 ICR25 ICR26 ICR27
0x5C ICR28 ICR29 ICR30 ICR31