Microcontroller User's Manual

MOTOROLA Chapter 8. System Control Module (SCM) 8-19
System Access Control Unit (SACU)
At reset, these on-chip modules are configured to have only supervisor read/write access
capabilities. Bit encodings for the ACCESS_CTRL field in the GPACR are shown in
Table 8-14. Table 8-15 shows the memory space protected by the GPACRs and the modules
mapped to these spaces.
Table 8-13. Grouped PeripheralAccess Control Register
(GPACR) Field Descriptions
Bits Name Description
7 LOCK This bit, once set, prevents subsequent writes to the GPACR. Any attempted write to the
GPACR generates an error termination and the contents of the register are not affected.
Only a system reset clears this flag.
6–4 — Reserved, should be cleared.
3–0 ACCESS_CTRL This 4-bit field defines the access control for the given memory region.
The encodings for this field are shown in Table 8-14.
Table 8-14. GPACR ACCESS_CTRL Bit Encodings
Bits Supervisor Mode User Mode
0000 Read / Write No Access
0001 Read No Access
0010 Read Read
0011 Read No Access
0100 Read / Write Read / Write
0101 Read / Write Read
0110 Read / Write Read / Write
0111 No Access No Access
1000 Read / Write / Execute No Access
1001 Read / Execute No Access
1010 Read / Execute Read / Execute
1011 Execute No Access
1100 Read / Write / Execute Read / Write / Execute
1101 Read / Write / Execute Read / Execute
1110 Read / Write Read
1111 Read / Write / Execute Execute