Microcontroller User's Manual

MOTOROLA Chapter 7. Power Management 7-17
Functional Description
Chip Configuration Module Enabled No Enabled No Stopped No
Power Management Enabled No Enabled No Stopped No
Clock Module Enabled Yes
2
Enabled Yes
2
Program Yes
2
Edge port Enabled Yes
2
Enabled Yes
2
Stopped Yes
2
Watchdog timer Program Yes
3
Program Yes
3
Stopped No
Programmable Interrupt Timers Enabled Yes
2
Program Yes
2
Stopped No
QADC Enabled Yes
2
Program Yes
2
Stopped No
General Purpose Timers Enabled Yes
2
Enabled Yes
2
Stopped No
FlexCAN Enabled Yes
2
Enabled Yes
2
Stopped No
Flash Control Module Enabled Yes
2
Enabled Yes
2
Stopped No
BDM Enabled Yes
4
Enabled Yes
4
Enabled Yes
4
JTAG Enabled No Enabled No Enabled No
1
“Program” Indicates that the peripheral function during the low-power mode is dependent on programmable bits in the
peripheral register map.
2
These modules can generate a interrupt which will exit a low-power mode. The CPU will begin to service the interrupt exception
after wakeup.
3
These modules can generate a reset which will exit any low-power mode.
4
The BDM logic is clocked by a separate TCLK clock. Entering halt mode via the BDM port exits any low-power mode. Upon exit
from halt mode, the previous low-power mode will be re-entered and changes made in halt mode will remain in effect.
Table 7-7. CPU and Peripherals in Low-Power Modes (continued)
Module
Peripheral Status
1
/ Wakeup Capability
Wait Mode Doze Mode Stop Mode