Microcontroller User's Manual

7-4 MCF5282 User’s Manual MOTOROLA
Memory Map and Registers
7.2.3.2 Low-Power Control Register (LPCR)
The LPCR controls chip operation and module operation during low-power modes.
Table 7-3. XLPM_IPL Settings
XLPM_IPL [2:0] Interrupts Level Needed to Exit Low-Power Mode
000 Any interrupt request exits low-power mode
001 Interrupt request levels [2-7] exit low-power mode
010 Interrupt request levels [3-7] exit low-power mode
011 Interrupt request levels [4-7] exit low-power mode
100 Interrupt request levels [5-7] exit low-power mode
101 Interrupt request levels [6-7] exit low-power mode
11x Interrupt request level [7] exits low-power mode
7 6543210
Field LPMD — STPMD — LVDSE —
Reset 0000_0010
R/W R/W
Address IPSBAR + 0x0011_0007
Figure 7-2. Low-Power Control Register (LPCR)
Table 7-4. LPCR Field Descriptions
Bits Name Description
7–6 LPMD Low-power mode select. Used to select the low-power mode the chip enters once
the ColdFire CPU executes the STOP instruction. These bits must be written prior
to instruction execution for them to take effect. The LPMD[1:0] bits are readable
and writable in all modes. Table 7-5 illustrates the four different power modes that
can be configured with the LPMD bit field.
5 — Reserved, should be cleared.
4–3 STPMD PLL/CLKOUT stop mode. Controls PLL and CLKOUT operation in stop mode as
shown in Table 7-6
2 — Reserved, should be cleared.
1 LVDSE LDV standby enable. Controls whether the PMM enters VREG Standby Mode
(LVD disabled) or VREG Pseudo-Standby (LVD enabled) mode when the PMM
receives a power down request. This bit has no effect if the RCR[LVDE] bit is a
logic 0.
1 VREG Pseudo-Standby mode (LVD enabled on power down request).
0 VREG Standby mode (LVD disabled on power down request).
0 — Reserved, should be cleared.