Microcontroller User's Manual

5-4 MCF5282 User’s Manual MOTOROLA
SRAM Programming Model
The ColdFire processor or an external emulator using the debug module can perform these
initialization functions.
5.3.3 SRAM Initialization Code
The following code segment describes how to initialize the SRAM. The code sets the base
address of the SRAM at 0x20000000 and then initializes the SRAM to zeros.
RAMBASE EQU $20000000 ;set this variable to $20000000
RAMVALID EQU $00000001
move.l #RAMBASE+RAMVALID,D0 ;load RAMBASE + valid bit into D0.
movec.l D0, RAMBAR ;load RAMBAR and enable SRAM
The following loop initializes the entire SRAM to zero
lea.l RAMBASE,A0 ;load pointer to SRAM
move.l #16384,D0 ;load loop counter into D0
SRAM_INIT_LOOP:
clr.l (A0)+) ;clear 4 bytes of SRAM
subq.l #1,D0 ;decrement loop counter
bne.b SRAM_INIT_LOOP ;if done, then exit; else continue
looping
5.3.4 Power Management
As noted previously, depending on the configuration defined by the RAMBAR, instruction
fetch and operand read accesses may be sent to the SRAM and cache simultaneously. If the
access is mapped to the SRAM module, it sources the read data and the unified cache access
is discarded. If the SRAM is used only for data operands, asserting the ASn bits associated
with instruction fetches can decrease power dissipation. Additionally, if the SRAM
contains only instructions, masking operand accesses can reduce power dissipation.
Table 5-2 shows some examples of typical RAMBAR settings.
Table 5-2. Typical RAMBAR Setting Examples
Data Contained in SRAM RAMBAR[7:0]
Code Only 0x2B
Data Only 0x35
Both Code And Data 0x21