Microcontroller User's Manual

xiv MCF5282 User’s Manual MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
20.3 Low-Power Mode Operation ............................................................................ 20-3
20.4 Signal Description............................................................................................. 20-3
20.4.1 GPTn[2:0] ..................................................................................................... 20-3
20.4.2 GPTn3........................................................................................................... 20-4
20.4.3 SYNCn.......................................................................................................... 20-4
20.5 Memory Map and Registers.............................................................................. 20-4
20.5.1 GPT Input Capture/Output Compare Select Register (GPTIOS) ................. 20-5
20.5.2 GPT Compare Force Register (GPCFORC)................................................. 20-6
20.5.3 GPT Output Compare 3 Mask Register (GPTOC3M).................................. 20-6
20.5.4 GPT Output Compare 3 Data Register (GPTOC3D).................................... 20-7
20.5.5 GPT Counter Register (GPTCNT) ............................................................... 20-7
20.5.6 GPT System Control Register 1 (GPTSCR1)............................................... 20-8
20.5.7 GPT Toggle-On-Overflow Register (GPTTOV).......................................... 20-9
20.5.8 GPT Control Register 1 (GPTCTL1)............................................................ 20-9
20.5.9 GPT Control Register 2 (GPTCTL2).......................................................... 20-10
20.5.10 GPT Interrupt Enable Register (GPTIE) .................................................... 20-10
20.5.11 GPT System Control Register 2 (GPTSCR2)............................................. 20-11
20.5.12 GPT Flag Register 1 (GPTFLG1)............................................................... 20-12
20.5.13 GPT Flag Register 2 (GPTFLG2)............................................................... 20-12
20.5.14 GPT Channel Registers (GPTCn)............................................................... 20-13
20.5.15 Pulse Accumulator Control Register (GPTPACTL) .................................. 20-13
20.5.16 Pulse Accumulator Flag Register (GPTPAFLG)........................................ 20-14
20.5.17 Pulse Accumulator Counter Register (GPTPACNT) ................................. 20-15
20.5.18 GPT Port Data Register (GPTPORT)......................................................... 20-16
20.5.19 GPT Port Data Direction Register (GPTDDR)........................................... 20-16
20.6 Functional Description.................................................................................... 20-17
20.6.1 Prescaler...................................................................................................... 20-17
20.6.2 Input Capture .............................................................................................. 20-17
20.6.3 Output Compare.......................................................................................... 20-17
20.6.4 Pulse Accumulator...................................................................................... 20-18
20.6.5 Event Counter Mode................................................................................... 20-18
20.6.6 Gated Time Accumulation Mode ............................................................... 20-19
20.6.7 General-Purpose I/O Ports.......................................................................... 20-19
20.7 Reset................................................................................................................ 20-21
20.8 Interrupts......................................................................................................... 20-21
20.8.1 GPT Channel Interrupts (CnF) ................................................................... 20-22
20.8.2 Pulse Accumulator Overflow (PAOVF)..................................................... 20-22
20.8.3 Pulse Accumulator Input (PAIF) ................................................................ 20-22
20.8.4 Timer Overflow (TOF) ............................................................................... 20-22